1. Field of the Invention
Embodiments of the invention relate generally to cache coherency, and more specifically, to maintaining relaxed coherency between different caches that may store the same cache lines.
2. Description of the Related Art
Conventional parallel processing architectures support execution of multiple threads and the multiple threads access memory through a single cache. Therefore, when a first thread writes data to a location in memory, the data is stored in the cache. When a second thread reads the same location from memory, the data is retrieved from the cache. Because the first thread and the second thread share the same cache, the first thread and the second thread see a consistent view of the memory.
When the single cache is replaced with a first cache and a second cache that are accessed by different portions of the multiple threads, a mechanism may be needed to maintain coherence between the first and second caches. For example, the first thread may write data to a location in memory and then the second thread may read the same location in the memory. If the first thread writes the data to the first cache and the second thread reads data from the second cache, the second thread is not guaranteed to read the data that was written by the first thread. A mechanism is needed to maintain coherence between the first cache and the second cache.
One mechanism that may used to maintain coherence between the first and second cache is to broadcast write operations for each of the multiple threads to both caches. A first drawback of this mechanism is that wires are needed to broadcast the write operations to both caches. A second drawback of this mechanism is that the total number of cache writes increases, thereby consuming bandwidth that could be used to perform other cache write operations or cache read operations.
Accordingly, what is needed in the art is an improved technique for maintaining coherence between a first cache and a second cache when different portions of multiple parallel threads access both caches.